FIG. 1 is an exploded view of a conventional chip package 100. The chip package 100 includes a memory die 101 and the logic die 102. In this example, the dies 101, 102 are stacked in the chip package 100 and communicate with each other using Through Silicon Vias (TSVs) 103. The TSVs 103 are vias extending through the semiconductor materials of each of the dies 101, 102.
The logic die 102 includes an External Bus Interface (EBI) 105, which is a memory controller and interface between the logic die 102 and the memory die 101. The memory die 101 includes memory cells 104, which store information as instructed by the EBI 105.
One difficulty with the chip package 100 is that functionality of the EBI 105 is not tested until dies 101, 102 are physically interfaced. In other words, if the number of interface signals are larger than what an external tester can support, the testing procedure includes checking functionality of the EBI 105 by using the EBI 105 to store information to the memory cells 104. The information can be read out from the memory cells 104 to verify that the information was stored correctly. Once the dies 101, 102 are physically interfaced in the package 100, it is not practical to salvage one of the dies 101, 102 separately from the other. Therefore, if testing reveals a problem with the EBI 105, the whole chip package 100 is scrapped, even if the memory die 102 is fully functional. In other words, the conventional testing procedure can result in undesirably high scrap costs.